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Find the real speed limit: FPGA CAD for chip-specific application delay measurement.

Ibrahim AhmedShuze ZhaoOlivier TrescasesVaughn Betz
Published in: FPL (2017)
Keyphrases
  • high speed
  • low cost
  • single chip
  • solid models
  • programmable logic
  • data acquisition
  • object oriented
  • high density
  • neural network
  • computer aided
  • computer aided design
  • power dissipation