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A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology.
Kaikai Liu
Ting An
Hao Cai
Lirida A. B. Naviner
Jean-François Naviner
Hervé Petit
Published in:
EUROCON (2013)
Keyphrases
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cost effective
noise tolerant
cost effectiveness
cmos technology
low cost
special case
low power
upper bound
design process
missing values
power consumption
multi valued
power dissipation
low voltage