Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking.
Jens SchönherrMartin FreibotheBernd StraubeJörg BormannPublished in: Theor. Comput. Sci. (2008)
Keyphrases
- steady state
- formal verification
- bounded model checking
- mixed signal
- vlsi circuits
- low power
- model checking
- multi channel
- markov chain
- queue length
- product form
- operating conditions
- explicit expressions
- temporal logic
- high speed
- cmos technology
- heavy traffic
- steady states
- state dependent
- arrival rate
- digital circuits
- service times
- image processing
- field effect transistors
- queueing networks
- low cost
- queueing model
- linear temporal logic
- power consumption
- multi agent systems