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C5: Cross-Cores Cache Covert Channel.

Clémentine MauriceChristoph NeumannOlivier HeenAurélien Francillon
Published in: DIMVA (2015)
Keyphrases
  • covert channel
  • processor core
  • security requirements
  • data access
  • query processing
  • operating system
  • prefetching
  • case study
  • open source
  • network traffic
  • main memory
  • memory access
  • dynamic random access memory