Power-Clock Gating in Adiabatic Logic Circuits.

Philip Teichmann Jürgen Fischer Stephan Henzler Ettore Amirante Doris Schmitt-Landsiedel

Published in: PATMOS (2005)

Keyphrases

logic circuits
power dissipation
power consumption
low power
clock gating
power reduction
functional decomposition
digital signal processing
tunnel diode
high speed
low cost
power saving
energy saving
gate array
energy efficiency
computer vision
finite state machines
image processing
case study