Via placement for minimum interconnect delay in three-dimensional (3D) circuits.
Vasilis F. PavlidisEby G. FriedmanPublished in: ISCAS (2006)
Keyphrases
- power dissipation
- three dimensional
- power consumption
- high speed
- low power
- digital signal processing
- cmos technology
- chip design
- logic circuits
- d objects
- vlsi circuits
- power reduction
- multi view
- image sequences
- analog circuits
- computed tomography
- circuit design
- image processing
- neural network
- depth map
- virtual reality
- x ray
- finite state machines
- low cost