Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits.

Ji-Yong Jeong Gil-Su Kim Jong-Pil Son Woo-Jin Rim Soo-Won Kim

Published in: PATMOS (2006)

Keyphrases

logic circuits
low voltage
cmos technology
power reduction
low power
power dissipation
power consumption
power management
leakage current
high speed
low cost
power line
power saving
digital signal processing
energy efficiency
design considerations
energy saving
design methodology
image sensor
data center