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Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions.
G. Edward Suh
Charles W. O'Donnell
Ishan Sachdev
Srinivas Devadas
Published in:
ISCA (2005)
Keyphrases
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single chip
low power
highly parallel
software implementation
low cost
signal processor
cmos image sensor
image sensor
embedded processors
high speed
power consumption
real time
efficient implementation
stream cipher