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A Performance Enhanced Dual-switch Network-on-chip Architecture.

Lian ZengXin JiangTakahiro Watanabe
Published in: IPSJ Trans. Syst. LSI Des. Methodol. (2015)
Keyphrases
  • network on chip
  • multi processor
  • routing algorithm
  • network simulator
  • packet switched
  • high speed
  • data transfer
  • single processor