A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS.
Jaewon LeeWoojae LeeSeongHwan ChoPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2012)
Keyphrases
- high speed
- low power
- cmos technology
- ultra low power
- power dissipation
- nm technology
- silicon on insulator
- power consumption
- metal oxide semiconductor
- computer simulation
- multipath
- low voltage
- phase locked loop
- single chip
- chip design
- decision feedback
- focal plane
- clock frequency
- mixed signal
- low cost
- ultra wideband
- digital signal processing
- social sciences
- real time
- low power consumption
- power management
- high density
- integrated circuit
- end to end