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FPGA-Based Hardware Accelerator for an Embedded Factor Graph with Configurable Optimization.
Indar Sugiarto
Cristian Axenie
Jörg Conradt
Published in:
J. Circuits Syst. Comput. (2019)
Keyphrases
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field programmable gate array
embedded systems
factor graphs
hardware implementation
hardware architecture
smart camera
graphical models
hardware design
message passing
belief propagation
probabilistic inference
probabilistic graphical models
bayesian networks
approximate inference