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A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 µm CMOS.
Arnoud P. van der Wel
Gerrit den Besten
Published in:
IEEE J. Solid State Circuits (2012)
Keyphrases
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high speed
data sets
data collection
data analysis
knowledge discovery
high quality
original data
raw data
image data
data mining techniques
input data
data points
database
data acquisition
data distribution
duty cycle
power consumption
missing data
computer systems
databases
end users
prior knowledge
data structure