An analog (7, 5) convolutional decoder in 65 nm CMOS for low power wireless applications.
Reza MerajiJohn B. AndersonHenrik SjölandViktor ÖwallPublished in: ISCAS (2011)
Keyphrases
- low power
- mixed signal
- cmos technology
- ultra low power
- vlsi architecture
- wireless transmission
- nm technology
- power consumption
- vlsi circuits
- low cost
- high speed
- cmos image sensor
- successive approximation
- image sensor
- single chip
- low voltage
- wireless networks
- low complexity
- wireless communication
- error concealment
- power dissipation
- silicon on insulator
- power reduction
- low density parity check
- digital signal processing
- wide dynamic range
- analog vlsi
- power management
- wifi
- digital circuits
- low power consumption
- circuit design
- distributed video coding
- delay insensitive
- metal oxide semiconductor
- analog to digital converter
- parallel processing