ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.
Hadi EsmaeilzadehSaeed ShamshiriPooya SaeediZainalabedin NavabiPublished in: Asian Test Symposium (2005)
Keyphrases
- low power
- low cost
- vlsi architecture
- power consumption
- high speed
- cmos technology
- mixed signal
- single chip
- power reduction
- real time
- nm technology
- digital signal processing
- signal processor
- hardware implementation
- vlsi circuits
- hardware and software
- high power
- hardware software co design
- low power consumption
- wireless transmission
- image sensor
- logic circuits
- low voltage
- gate array
- delay insensitive
- field programmable gate array
- general purpose
- functional units
- digital camera
- parallel processing