A 9-bit 100-MS/s flash-SAR ADC without track-and-hold circuits.

Young-Kyun Cho Jae Ho Jung Kwang Chun Lee

Published in: ISWCS (2012)

Keyphrases

analog to digital converter
random access memory
synthetic aperture radar
shift register
sar images
logic synthesis
high speed
sar imagery
image reconstruction
parameter estimation
digital circuits
logic circuits
mixed signal
delay insensitive
multi channel
pac man
maximum likelihood