A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks.
Guoyue JiangZhaolin LiFang WangShaojun WeiPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2015)
Keyphrases
- low power
- low latency
- high speed
- high bandwidth
- single chip
- low cost
- low power consumption
- power consumption
- digital signal processing
- logic circuits
- mixed signal
- cmos technology
- real time
- mobile nodes
- image sensor
- ultra low power
- signal processor
- high throughput
- data acquisition
- high density
- nm technology
- stream processing
- highly efficient
- efficient implementation
- data processing
- computational complexity