A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting.
Manxin LiCalvin Yoji LeePraveen Kumar VenkatachalaAhmed ElShaterYuichi MiyaharaKazuki SobueKoji TomiokaUn-Ku MoonPublished in: IEEE J. Solid State Circuits (2023)