Analyzing LTL Model Checking Techniques for Plan Synthesis and Controller Synthesis (Work in Progress).
Sylvain KerjeanFroduald KabanzaRichard St-DenisSylvie ThiébauxPublished in: Electron. Notes Theor. Comput. Sci. (2006)
Keyphrases
- model checking
- controller synthesis
- temporal logic
- bounded model checking
- closed loop
- planning domains
- formal verification
- finite state
- linear temporal logic
- temporally extended goals
- formal specification
- control system
- model checker
- temporal properties
- symbolic model checking
- verification method
- formal methods
- automated verification
- transition systems
- linear time temporal logic
- multi agent
- computation tree logic
- reactive systems
- timed automata
- control algorithm
- concurrent systems
- epistemic logic
- ai planning
- pspace complete
- controller design
- learning algorithm
- temporally extended
- modal logic
- search algorithm