Minimum-Area Sequential Budgeting for FPGA.
Chao-Yang YehMalgorzata Marek-SadowskaPublished in: ICCAD (2003)
Keyphrases
- high speed
- hardware implementation
- global minimum
- field programmable gate array
- hardware design
- real time
- low cost
- minimum cost
- spanning tree
- sequential data
- digital signal
- verilog hdl
- square error
- parallel hardware
- software implementation
- hardware architecture
- single chip
- decision trees
- artificial intelligence
- databases