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Gate stack resistance and limits to CMOS logic performance.
Richard A. Wachnik
Sungjae Lee
Li-Hong Pan
Ning Lu
Hongmei Li
Raphael Bingert
Mai Randall
Scott K. Springer
Christopher S. Putnam
Published in:
CICC (2013)
Keyphrases
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delay insensitive
cmos technology
power consumption
high speed
modal logic
random access memory
low power
low cost
chip design
real time
nm technology
flip flops
asynchronous circuits
data sets
analog vlsi
defeasible logic
low voltage
predicate logic
classical logic
field effect transistors
floating gate
logic programming
neural network
gate dielectrics