Gate stack resistance and limits to CMOS logic performance.
Richard A. WachnikSungjae LeeLi-Hong PanNing LuHongmei LiRaphael BingertMai RandallScott K. SpringerChristopher S. PutnamPublished in: CICC (2013)
Keyphrases
- delay insensitive
- cmos technology
- power consumption
- high speed
- modal logic
- random access memory
- low power
- low cost
- chip design
- real time
- nm technology
- flip flops
- asynchronous circuits
- data sets
- analog vlsi
- defeasible logic
- low voltage
- predicate logic
- classical logic
- field effect transistors
- floating gate
- logic programming
- neural network
- gate dielectrics