Efficient STT-RAM last-level-cache architecture to replace DRAM cache.
Fazal HameedChristian MenardJerónimo CastrillónPublished in: MEMSYS (2017)
Keyphrases
- main memory
- memory subsystem
- cache conscious
- memory access
- memory hierarchy
- prefetching
- database management systems
- data structure
- dynamic random access memory
- real time
- data access
- cache misses
- instruction set
- caching scheme
- data management
- access patterns
- design considerations
- application level
- multithreading
- management system
- computer architecture
- flash memory
- external memory
- hit rate
- index structure
- query processing