Bottom-up visual attention model based on FPGA.

Francisco Barranco Javier Díaz Begoña del Pino Eduardo Ros

Published in: ICECS (2012)

Keyphrases

visual attention
hardware implementation
field programmable gate array
low cost
high speed
real time image processing
real time
case study
data driven
signal processing
computational models
model free
single chip
verilog hdl