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A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro.

Meng-Fan ChangChe-Wei WuChia-Chen KuoShin-Jang ShenSue-Meng YangKu-Feng LinWen-Chao ShenYa-Chin KingChorng-Jung LinYu-Der Chih
Published in: IEEE J. Solid State Circuits (2013)
Keyphrases
  • low voltage
  • random access memory
  • real time
  • optical flow
  • digital images
  • design process
  • power line