Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory.
Shreyash PatelYoungBae KimKen ChoiPublished in: ISOCC (2018)
Keyphrases
- low power
- power consumption
- single chip
- low power consumption
- low cost
- power dissipation
- high speed
- cmos technology
- vlsi architecture
- logic circuits
- power reduction
- gate array
- digital signal processing
- memory hierarchy
- mixed signal
- nm technology
- main memory
- real time
- high power
- analog to digital converter
- dynamic random access memory
- computational power
- memory subsystem
- design process
- power management
- data transmission