An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures.
C. K. EemJ. W. ChongPublished in: ASP-DAC (1999)
Keyphrases
- high speed
- vlsi circuits
- signal processing
- gate array
- computationally efficient
- hybrid approaches
- power dissipation
- data driven
- significant improvement
- image segmentation
- image processing
- database
- single chip
- analog circuits
- vlsi design
- file organization
- information retrieval
- analog vlsi
- neural network
- chip design
- data sets