Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction.
Theodoros GiannopoulosVassilis PaliourasPublished in: PATMOS (2005)
Keyphrases
- low power
- high speed
- ofdm system
- single chip
- vlsi circuits
- gate array
- vlsi architecture
- power consumption
- low cost
- power dissipation
- high power
- power reduction
- estimation algorithm
- mixed signal
- wireless communication
- wireless transmission
- communication systems
- multipath
- image sensor
- low power consumption
- logic circuits
- digital signal processing
- bit error rate
- cmos technology
- signal processing
- fading channels
- delay insensitive
- end to end