FPGA Optimizations for a Pipelined Floating-Point Exponential Unit.
Nikolaos AlachiotisAlexandros StamatakisPublished in: ARC (2011)
Keyphrases
- floating point
- fixed point
- power reduction
- parallel architecture
- square root
- high speed
- field programmable gate array
- floating point arithmetic
- interval arithmetic
- hardware implementation
- instruction set
- fast fourier transform
- hardware architecture
- sparse matrices
- image processing
- low cost
- hardware and software
- signal processing
- general purpose