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Architectural optimization for low-power nonpipelined asynchronous systems.
Luis A. Plana
Steven M. Nowick
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (1998)
Keyphrases
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low power
power consumption
high speed
low cost
high power
logic circuits
delay insensitive
vlsi circuits
distributed systems
single chip
digital signal processing
cmos technology
wireless transmission