Architectural optimization for low-power nonpipelined asynchronous systems.

Luis A. Plana Steven M. Nowick

Published in: IEEE Trans. Very Large Scale Integr. Syst. (1998)

Keyphrases

low power
power consumption
high speed
low cost
high power
logic circuits
delay insensitive
vlsi circuits
distributed systems
single chip
digital signal processing
cmos technology
wireless transmission