Noise and Jitter in CMOS Digitally Controlled Delay Lines.

Monica Figueiredo Rui L. Aguiar

Published in: ICECS (2006)

Keyphrases

end to end delay
power consumption
low cost
straight line
noise reduction
noise level
power dissipation
noisy data
signal to noise ratio
low power
vlsi circuits
delay insensitive
image noise
additive noise
median filter
packet loss
line segments
hough transform
missing data
high speed