Design and Implementation of Low-Power Hardware Architecture With Single-Cycle Divider for On-Line Clustering Algorithm.
Tse-Wei ChenMakoto IkedaPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2013)
Keyphrases
- hardware architecture
- low power
- vlsi architecture
- low cost
- hardware implementation
- cmos technology
- power consumption
- low power consumption
- hardware architectures
- single chip
- clustering algorithm
- ultra low power
- logic circuits
- high speed
- digital signal processing
- gate array
- high power
- efficient implementation
- mixed signal
- field programmable gate array
- delay insensitive
- wireless transmission
- vlsi circuits
- xilinx virtex
- power dissipation
- vlsi implementation
- digital circuits
- power reduction
- design methodology