SAR TDC architecture for one-shot timing measurement with full digital implementation.
Yuki OzawaTakashi IdaShotaro SakuraiRichen JiangRino TakahashiHaruo KobayashiRyoji ShiotaPublished in: ISPACS (2017)
Keyphrases
- layered architecture
- design considerations
- hardware implementation
- design methodology
- circuit design
- architectural design
- management system
- hardware architecture
- fpga technology
- vlsi implementation
- vlsi architecture
- parallel computers
- sigma delta
- hardware architectures
- application programming interface
- cmos technology
- low power
- efficient implementation
- parameter estimation