High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis.
Ashkan Hosseinzadeh NaminKarl LeboeufRoberto MuscedereHuapeng WuMajid AhmadiPublished in: IET Circuits Devices Syst. (2010)
Keyphrases
- hardware implementation
- high speed
- parallel architecture
- signal processing
- software implementation
- efficient implementation
- processing elements
- dedicated hardware
- fpga implementation
- pipelined architecture
- image processing algorithms
- hardware architecture
- field programmable gate array
- parallel processing
- parallel implementation
- hardware design
- memory management
- shift register
- computer architecture
- pipeline architecture
- real time