Indirect VLIW memory allocation for the ManArray multiprocessor DSP.
Nikos PitsianisGerald G. PechanekPublished in: SIGARCH Comput. Archit. News (2003)
Keyphrases
- level parallelism
- signal processing
- digital signal processing
- digital signal processor
- database machines
- highly parallel
- verilog hdl
- multiprocessor systems
- high speed
- single processor
- real time image processing
- computer vision
- data sets
- database
- embedded systems
- data flow
- distributed memory
- scheduling algorithm
- response time
- neural network
- systolic array
- shared memory multiprocessor