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Hierarchy machine set-up for multi-pass lot scheduling at semiconductor assembly and test facilities.

Youngbum HurJonathan F. BardRodolfo Chacon
Published in: Int. J. Prod. Res. (2019)
Keyphrases
  • hierarchical structure
  • higher level
  • parallel machines
  • wafer fabrication
  • real time
  • feature set
  • test cases
  • scheduling algorithm