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Impolite High Speed Interfaces with Asynchronous Pulse Logic.
Merritt Miller
Carrie Segal
David McCarthy
Aditya Dalakoti
Prashansa Mukim
Forrest Brewer
Published in:
ACM Great Lakes Symposium on VLSI (2018)
Keyphrases
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high speed
shift register
low power
delay insensitive
asynchronous circuits
gigabit ethernet
user interface
logic programming
modal logic
frame rate
hardware implementation
random number generator
high speed networks
multi valued
ultra wideband
predicate logic
computational properties
knowledge base
expert systems