A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning.
Hidenori SatoAkira OnozawaHiroaki MatsudaPublished in: ED&TC (1996)
Keyphrases
- high speed
- duty cycle
- routing algorithm
- d mesh
- power consumption
- interconnection networks
- ad hoc networks
- routing problem
- routing protocol
- electronic circuits
- shortest path
- network topology
- circuit design
- analog circuits
- real time
- load balance
- mesh generation
- low power
- triangle mesh
- three dimensional
- travel distance
- partitioning algorithm
- power dissipation
- network structure