A low power 100 Gbps DP-QPSK receiver using analog domain signal processing.
Nandakumar NambathAnita GuptaShalabh GuptaPublished in: ICNC (2013)
Keyphrases
- low power
- signal processing
- mixed signal
- vlsi architecture
- power consumption
- digital signal processing
- low cost
- high speed
- signal processor
- single chip
- vlsi circuits
- high power
- wireless transmission
- image processing
- dynamic programming
- logic circuits
- low power consumption
- image sensor
- computer vision
- pattern recognition
- cmos technology
- power reduction
- multi channel
- computer simulation
- real time
- gate array