Compiler-managed partitioned data caches for low power.
Rajiv A. RavindranMichael L. ChuScott A. MahlkePublished in: LCTES (2007)
Keyphrases
- low power
- partitioned data
- power consumption
- low cost
- high speed
- privacy preserving
- general purpose
- single chip
- wireless transmission
- high power
- gate array
- low power consumption
- logic circuits
- digital signal processing
- vlsi architecture
- power dissipation
- cmos technology
- delay insensitive
- hardware and software
- power reduction
- mixed signal
- real time