A Low Power Test Pattern Generator for BIST.

Shaochong Lei Feng Liang Zeye Liu Xiaoying Wang Zhen Wang

Published in: IEICE Trans. Electron. (2010)

Keyphrases

low power
pattern generator
power consumption
low cost
high speed
high power
vlsi architecture
single chip
wireless transmission
low power consumption
logic circuits
vlsi circuits
digital signal processing
delay insensitive
multi modal
built in self test
general purpose
cmos technology
image sensor
gate array