A massively scaleable decoder architecture for low-density parity-check codes.
Anand SelvarathinamGwan ChoiKrishna NarayananAchal PrabhakarEuncheol KimPublished in: ISCAS (2) (2003)
Keyphrases
- low density parity check
- ldpc codes
- decoding algorithm
- error correction
- vlsi architecture
- channel coding
- distributed video coding
- message passing
- low complexity
- physical layer
- low power
- channel capacity
- turbo codes
- rate allocation
- error detection
- joint source channel coding
- error correcting
- image transmission
- rate distortion
- unequal error protection
- vlsi implementation
- error resilience
- signal to noise ratio
- data hiding