Accelerating The Vvc Decoder For Vector Length Agnostic Simd Architectures.
Yassin KaddarAngela PohlBen H. H. JuurlinkPublished in: ICME (2020)
Keyphrases
- parallel architectures
- parallel algorithm
- single instruction multiple data
- successive approximation
- low complexity
- error concealment
- array processor
- neural network
- parallel processing
- feature vectors
- vector space
- massively parallel
- fixed length
- vector data
- video coding
- vector quantization
- video data
- alphabet size
- processor array
- feature space