A Scalable Built-in Self-test/Self-diagnosis Architecture for 2D-Mesh based Chip Multiprocessor Systems.

Shu-Yen Lin Chan-Cheng Hsu An-Yeu Wu

Published in: ISCAS (2009)

Keyphrases

multiprocessor systems
built in self test
multithreading
vlsi implementation
integrated circuit
access patterns
analog vlsi
fine grained
coarse grained
distributed memory
memory efficient
information retrieval
bayesian networks
low cost
highly efficient
highly scalable