Design of Low-Power WiNoC with Congestion-Aware Wireless Node.
Yiming OuyangZhe LiKun XingZhengfeng HuangHuaguo LiangJianhua LiPublished in: J. Circuits Syst. Comput. (2018)
Keyphrases
- low power
- ultra low power
- single chip
- low cost
- power consumption
- low power consumption
- wireless transmission
- high speed
- logic circuits
- digital signal processing
- vlsi architecture
- gate array
- cmos technology
- power dissipation
- mixed signal
- wireless networks
- high power
- power reduction
- design methodology
- error correction
- nm technology
- design process