Reliable low-power design in the presence of deep submicron noise (embedded tutorial session).
Naresh R. ShanbhagKrishnamurthy SoumyanathSamuel MartinPublished in: ISLPED (2000)
Keyphrases
- low power
- single chip
- low cost
- power consumption
- low power consumption
- high speed
- mixed signal
- vlsi circuits
- vlsi architecture
- logic circuits
- digital signal processing
- gate array
- cmos technology
- power dissipation
- embedded systems
- wireless transmission
- ultra low power
- high power
- nm technology
- power reduction
- design process
- real time
- design methodology
- multi channel
- hardware and software
- signal processing