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An Eight-Phase 40GHz RTWO in 28nm CMOS with Phase Noise Reduction Via Head and Tail Filtering.
Salvatore Galeone
Michael Peter Kennedy
Karim Ahmed
Hyman Shanan
Mike Keaveney
Published in:
ICECS (2019)
Keyphrases
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high speed
power consumption
clock gating
cmos technology
low power
low cost
silicon on insulator
metal oxide semiconductor
nm technology
real time
reduction method
phase unwrapping
learning phase
filtering algorithm
multiresolution
heavy tailed
power reduction
delay insensitive
vlsi circuits
frequency band