Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer.
Hossam A. ElGindyMartin MiddendorfHartmut SchmeckBernd SchmidtPublished in: FPL (2000)
Keyphrases
- field programmable gate array
- hardware implementation
- smart camera
- reconfigurable hardware
- low cost
- embedded systems
- parallel computing
- fpga implementation
- buffer size
- reconfigurable architecture
- closed world
- hardware software
- computing systems
- real time
- image processing algorithms
- virtual memory
- operating system
- motion estimation
- evolutionary algorithm
- case study
- image processing
- neural network