A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN.
Sandipan KunduErkan AlpmanJulia Hsin-Lin LuHasnain LakdawalaJeyanandh ParameshByunghoo JungSarit ZurEshel GordonPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2015)
Keyphrases
- analog to digital converter
- power consumption
- clock gating
- low power
- mixed signal
- linear programming
- image sensor
- cmos technology
- nm technology
- high speed
- power supply
- linear program
- synthetic aperture radar
- optimal solution
- metal oxide semiconductor
- sar images
- low cost
- sigma delta
- circuit design
- parameter estimation
- power reduction
- cmos image sensor
- clock frequency
- wireless networks
- quality of service