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A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET.
Wei-Chih Chen
Shu-Chun Yang
Yu-Nan Shih
Wen-Hung Huang
Chien-Chun Tsai
Kenny Cheng-Hsiang Hsieh
Published in:
VLSI Circuits (2019)
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