A timing analysis algorithm for circuits with level-sensitive latches.
Jin-Fuw LeeDonald T. TangChak-Kuen WongPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1996)
Keyphrases
- learning algorithm
- preprocessing
- k means
- worst case
- times faster
- computational complexity
- experimental evaluation
- high accuracy
- expectation maximization
- optimization algorithm
- segmentation algorithm
- particle swarm optimization
- simulated annealing
- improved algorithm
- single pass
- computational cost
- least squares
- cost function
- significant improvement
- optimal solution
- dynamic programming
- reinforcement learning
- neural network
- estimation algorithm
- genetic algorithm
- memory requirements
- similarity measure
- path planning
- matching algorithm
- tree structure
- bayesian networks
- theoretical analysis
- computationally efficient
- association rules
- search space
- data sets