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A Low-Power Low-Complexity Multi-Standard Digital Receiver for Joint Clock Recovery and Carrier Frequency Offset Calibration.
Ye Zhang
Jan Henning Mueller
Bastian Mohr
Stefan Heinen
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2014)
Keyphrases
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low complexity
low power
power consumption
high speed
vlsi architecture
mixed signal
low cost
motion estimation
computational complexity
distributed video coding
low density parity check
mimo systems
multiple description coding
multiple input multiple output
video streaming
cmos technology